FIG. 4 is a block diagram showing internal configuration of a communication system based on the conventional technology. In the communication system shown in this figure, a master unit 50 and a slave unit 60 are connected to each other with an extension bus 70 , and data communication between the master unit 50 and the slave unit 60 is executed through the extension bus 70.
The master unit 50 has the configuration in which a main memory 51 for a master unit and a reset signal generating section 53 are connected to a microprocessor 52 for a master unit with a bus. This master unit 50 provides centralized controls over the entire system by means of data communications between the microprocessor 52 for a master unit and each unit inside or an external slave unit 60 connected thereto.
The main memory 51 for a master unit comprises a ROM not shown herein with control programs such as initializing programs enabling operation of the master unit 50 or a RAM not shown herein and used for applications in a work area or the like stored therein. The microprocessor 52 for a master unit accesses the ROM or RAM not shown herein in the main memory 51 for a master unit and executes computing and control sequences.
The reset signal generating section 53 is connected to the microprocessor 52 for a master unit in the master unit 50 as well as to the slave unit 60 (a microprocessor 62 for a slave unit described hereinafter) outside the master unit 50 with a signal line 71 provided apart from the extension bus 70. This reset signal generating section 53 generates reset signals RS1 and RS2 each for system reset, supplies the reset signal RS1, one of the reset signals generated as described above, via the signal line 72 to the microprocessor 52 for a master unit, and also supplies the reset signal RS1, other one of the reset signals described above, via the signal line 71 to the microprocessor 62 for a slave unit described later.
The slave unit 60 has the configuration in which a main memory 61 for a slave unit is connected via a bus to the microprocessor 62 for a slave unit. This slave unit 60 is controlled according to data transmitted from the master unit 50 via the extension bus 70 or the signal line 71.
The main memory 61 for a slave unit stores therein various types of control program in a state where the control programs can be accessed from the microprocessor 62 for a slave unit. The microprocessor 62 for a slave unit controls the entire slave unit 60 according to each control program stored in the main memory 61 for a slave unit.
Next description is made for operations. In the communication system shown in FIG. 4, when a power for the system is turned ON, the reset signal generating section 53 determines that a voltage in each unit has reached a level allowing operation thereof, and releases the reset signal RS1 for the master unit and the reset signal RS2 for the slave unit each having been generated.
After the reset signals RS1 and RS2 are released, each of the master unit 50 and slave unit 60 starts initialization under control by the microprocessor 52 for a master unit and the microprocessor 62 for a slave unit respectively.
For instance, in the master unit 50, the microprocessor 52 for a master unit executes an initialization program stored in the main memory 51 for a master unit and initializes inside of the master unit 50. Also in the slave unit 60, the microprocessor 62 for a slave unit executes an initialization program stored in the main memory 61 for a slave unit and initializes inside of the slave unit 60.
When the master unit 50 finishes initialization, it starts access via the extension bus 70 to the slave unit 60 by sending a data send/receive request or other, so that the slave unit 60 sends a response to the send/receive request from the master unit 50.
Next description is made for a concrete example of use of the communication system shown in FIG. 4. FIG. 5 is a block diagram showing concrete configuration of a communication system based on the conventional technology. The communication system shown in the figure is a more particularized one from the communication system shown in FIG. 4. A programmable controller 50a (described as PLC hereinafter) for managing I/O control at a cite of FA (factory automation) or the like is applied to the master unit 50, and a personal computer unit 60a (described as PC unit hereinafter) having an internal architecture equivalent to that of a personal computer is applied to the slave unit 60.
The PLC 50a has the configuration in which an error detecting section 54 and an alarm output section 55 are furthermore added to internal configuration of the master unit 50 described above. The error detecting section 54 is connected to an internal bus connected to the microprocessor 52 for a master unit, detects an error, and outputs a error detection signal to the alarm output section 55 in the downstream. When the alarm output section 55 receives the error detection signal from the error detecting section 54, it outputs an alarm.
The PC unit 60a has the configuration in which a hard disk drive 63 (described as HDD hereinafter) for building a disk system is furthermore added to the internal configuration of the slave unit 60 described above, and a DRAM 61a for a slave unit is applied to the main memory 61 for a slave unit.
The HDD 63 stores operating systems (described as OS hereinafter) each working as software for starting the microprocessor 62 for a slave unit or various types of application program working according to this OS 64.
The DRAM 61a for a slave unit stores therein OS 64 or various types of application program stored in the HDD 63 according to controls by the microprocessor 62 for a slave system.
Next description is made for operations. In the PLC 50a shown in FIG. 5, the microprocessor 52 for a master unit executes initialization after the reset signal RS1 detected from the reset signal generating section 53 is released. So the PC unit 60a, connected to the PLC 50a, finishes initialization of the internal section before initialization of the PLC 50a is complete, and is waiting for access from the PLC 50a at a point in time when initialization of the PLC 50a is finished.
In the communication system shown in FIG. 5, the slave unit 60 stores the OS 64 or various types of application programs in itself like an example in the PC unit 60a, so that it generally manages the control programs by storing them in the HDD 63 having a large memory capacity.
For this reason, when the reset signal RS2 is released, the PC unit 60a executes initialization, namely stores the various programs in the DRAM 61a for a slave unit. In other words, in this initialization step, access to the HDD 63 is executed for reading out the OS 64 or the various application programs.
As described above, when the PC unit 60a is initialized, access to the hard disk is required, and the access time becomes far longer as compared to a period of time required for access to a ROM or a RAM in the PLC 50a. For this reason, in the PC unit 60a, the access time may sometimes becomes several minutes in contrast to several seconds in a case of the PLC 50a, and thus the time required for initialization of the PC unit 60a is substantially longer than that required for the PLC 50a.
In the communication system shown in FIG. 5, when the system power is turned ON, or when the hardware reset is released, the PLC 50a and the PC unit 60a start initialization respectively.
Then when initialization of the PLC 50a is finished, at this point of time initialization of the PC unit 60a has not been finished. For this reason, even if the PLC 50a sends a data send/receive request to the PC unit 60a, as the PC unit 60a is still in the process of initialization, it can not return a response.
In the case as described above, the error detecting section 54 provided in the PLC 50a checks a response time after access, and in a case where there is no response even if a preset period of time for response has passed, the error detecting section 54 determines that an error has occurred in the PC unit 60a.
The error detecting section 54 supplies an error detection signal to the alarm output section 55 according to a result of the determination that an error has occurred in the PLC unit 60a and makes the latter output an alarm, and also reports to the microprocessor 52 for a master unit that operation of the entire system is stopped for security.
In the conventional technology, because of the difference in a period of time required for initialization between the PLC 50a and the PC unit 60a, sometimes the entire communication system may be stopped due to delay in initialization of the PC unit 60a.
Under the circumstances as described above, in recent years, there has been a communication system in which the PC unit 60a can be initialized earlier than the PLC 50a by incorporating a delay means such as a software timer in the PLC 50a to make initialization of the PLC 50a later than that of the PC unit 60a.
As the technologies similar to that described above, there are those disclosed in Japanese Patent Laid-Open Publication No. HEI 1-205312, Japanese Patent Laid-Open Publication No. SHO 63-121966, and Japanese Patent Laid-Open Publication No. HEI 4-301952.
Japanese Patent Laid-Open Publication No. HEI 1-20531 discloses a technology for maintaining a reset state of a system where a reset state of a system (master unit) is not released even if reset of a slave unit is released, before passage of a prespecified period of time.
Japanese Patent Laid-Open Publication No. SHO 63-1211966 discloses the technology to delay release of reset of a host CPU (master unit) than release of reset of a slave CPU (slave unit) by using a delay circuit. Japanese Patent Laid-Open Publication No. HEI 4-301952 discloses the technology for a slave unit to execute reset and initialization of its hang-up according to passage of time set by a timer.
In addition to the similar technologies described above, there is, for instance, a technology disclosed in Japanese Patent Laid-Open Publication HEI 4-240946. This publication discloses the technology for controlling initialization of a main station (master unit) which is not working by a slave unit during the normal system operation.
In communication systems based on the conventional technology, as disclosed in each of the patent publications described above, a delay means such as a timer is incorporated for delaying initialization of a master unit, so that a delay time must be set according to a time for initialization corresponding to a memory capacity used by the OS 64 or various types of applications stored in the HDD 63 like in a case of the PC unit 60a, and in this case there is a problem related to the hardware that it is difficult to set an optimal delay time for system initialization.
To solve the problems as described above, a communication system is conceivable in which the PLC 50a executes polling processing to the PC unit 60a to make up a stand-by state until the system is normally initialized from a point of time when initialization of the PLC 50a has been finished until a point of time when the PC unit 60a becomes ready for accepting access by the PLC 50a.
However, for a communication system in which polling processing is executed, a control program for executing the polling processing is required for the PLC 50a, there is a problem related to software that the processing becomes complicated.